The present invention relates to a CMIS (complementary metal-insulated semiconductor) memory decoder, more particularly, to a CMIS memory decoder which produces an output signal for selecting a set of 2.sup.m word lines.
A decoder is one of the important peripheral members for driving a ROM (read-only memory) or a RAM (random access memory). The decoder is usually fabricated by CMIS devices.
In a typical type of memory comprised of a plurality of rows and columns, decoder type units of the CMIS memory decoder are provided at every row (word line) and every column (bit line). For example, each row is accessed by an address signal through its own decoder unit.
The latest trend is, to use highly integrated large-capacity ROM's or RAM's. In such highly integrated large-capacity memories, each memory cell must be constructed extremely small in size, and, accordingly, the distance between each adjacent row must also be made extremely narrow. It becomes very difficult to properly place the decoder unit for each row because there is not enough space to accommodate each decoder unit between each adjacent row. Further, it also becomes difficult to obtain high-speed ROM's or RAM's. Thus, it is necessary to overcome the above-mentioned difficulties. One of the most useful methods for overcoming the above difficulties has already been proposed. In that method, the decoder produces an output signal for selecting each set of 2.sup.m word lines, where the symbol m denotes a positive integer and m is actually defined as being 1 or 2. A selection of each set of 2.sup.1 word lines or a selection of 2.sup.2 word lines is relatively easy to apply to a RAM or CMIS memory. This is because such a RAM or CMIS memory usually needs a large space, such as 50 .mu.m.times.50 .mu.m, for placement of each memory cell. Accordingly, it is easy to place the CMIS decoder units between each adjacent row.
However, it is not easy for the CMIS decoder, according to the aforesaid method for selecting each set of 2.sup.1 or 2.sup.2 word lines, to be applied to a ROM, especially to a ROM constructed in the form of a so-called one-transistor-cell arrangement. In such a ROM, each memory cell can be formed in a space 7.5 .mu.m.times.8.5 .mu.m in size. Accordingly, each of the decoder units comprising the CMIS decoder must also be placed in a 7.5 .mu.m.times.8.5 .mu.m space. Further, in such a ROM, the CMIS decoder should be driven by the method for selecting each set of 2.sup.2 word lines, because said method is more effective in reducing the size of each memory cell than the method for selecting each set of 2.sup.1 word lines.